The present invention relates generally to integrated circuits, and more particularly, to a flip-flop circuit having resistive poly routing.
Flip-Flop (FF) performance is a crucial factor for high performance SOCs, not just in terms of functional operation, but also for layout and routing. Reducing metal connections inside a FF cell, which is replicated many times within a chip, can make available more metal routing tracks over the FFs, which allows for higher SOC routability.
A conventional master-slave FF (MS-FF) includes two latches with each latch holding data by using a feedback loop. The design of a MS-FF gives rise to at last two issues. First, the feedback loop will slow data changing from one state to another. Second, the internal inverted clock and non-inverted clock are not aligned with each other, which causes a relatively large setup and hold time.
It would be advantageous to have a FF design that overcomes the above-mentioned issues.